Post-Develop Inspection (PDI): Catching Lithography Defects Before Etch Commit
Averroes
Oct 31, 2026
Post-develop inspection (PDI), also called after-develop inspection (ADI), is the inline check of the developed photoresist pattern before etch in semiconductor manufacturing. It catches the defects develop creates or reveals, scumming, bridging, pattern collapse, missing pattern and residue, while the pattern still exists only in resist. A wafer that fails PDI can be stripped, recoated and re-exposed; the same defect found after etch is permanent. That is what makes PDI the gate that decides etch commit.
PDI is the middle gate of the Stage 03 inspection chain in the semiconductor manufacturing process, between the resist coat check and post-etch inspection. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps the develop defects, the macro and micro methods that catch them, and the economics that make this gate’s judgment worth more than any other in the patterning loop.
Key Notes
PDI and ADI are the same gate under two names: the inspection of developed resist before etch commit.
PDI runs in two layers: macro defect inspection across the whole wafer, and micro patterned inspection on the dies.
Misalignment is not a PDI defect. Overlay error is measured by metrology on dedicated targets, alongside but separate from defect inspection.
A reject at PDI costs one strip and recoat. The same defect found after etch is cut into the wafer for good.
PDI, ADI and the Three-Gate Chain
Post-develop inspection and after-develop inspection name the same gate: PDI is the common term in fab operations, ADI in litho-cell and metrology contexts. Both mean the defect check that runs once the exposed resist image has been developed into a physical pattern, and both end in the same decision: release the wafer to etch, rework it, or hold it.
The gate sits in the middle of a chain of three. Photoresist inspection checks the coated film before exposure, so coating defects never reach the scanner. PDI checks the developed pattern before etch, which this page covers. Post-etch inspection verifies the transferred pattern after it, when rework is no longer possible. Each gate exists because the step before it can fail in ways the step after it makes permanent.
Two measurements run on the same developed wafer and get blended into PDI, and neither belongs to it. Overlay, the alignment of this layer’s pattern to the one below, is measured by overlay metrology on dedicated targets; a misaligned wafer is a metrology finding, not an inspection detection, even though it triggers the same rework. And ADI CD, the linewidth measurement on developed resist, belongs to critical dimension metrology. PDI is the defect side of the develop check: it answers whether the pattern is intact, not how wide or how aligned it is.
Develop itself is the final step of the photolithography process, and PDI inspects its output. Everything the exposure and develop sequence can get wrong converges on this one surface.
Develop defects at a glance
Defect
Looks Like
Caught By
Disposition
Resist scumming
Residue in clear spaces
Macro scan, micro inspection
Rework
Bridging
Resist joining separate lines
Micro die-to-die
Rework
Missing pattern
Features absent or broken
Macro and micro
Rework
Pattern collapse
Fallen, leaning lines
Macro regions, micro detail
Rework
Developer residue
Stains, satellite spots
Macro scan, review
Reclean or rework
Revealed hotspots
Thinned, deformed features
Micro, e-beam sampling
Hold, feedback to scanner
The chain makes the gate’s position visible: PDI is the last point where the loop still runs backward. Past etch, the arrow only points forward.
What Defects Does Develop Create or Reveal?
Develop defects are flaws in the resist pattern that appear when the exposed image is developed: some created by the develop step itself, some printed earlier at the scanner and first visible now. Both kinds surface on the same wafer at the same gate, which is why PDI data feeds back in two directions.
The gallery carries the section’s split: some of these defects were made at develop, and some were made at exposure and only became visible here.
Resist Scumming and Incomplete Develop
Resist scumming is residual resist left in spaces that should have developed clear. It comes from under-develop, exhausted or weak developer, insufficient develop time, or under-exposure that left the resist less soluble than intended. A scummed space etches as a blocked or narrowed feature, so a contact hole with scum at its base becomes a failed connection one step later.
Bridging and Missing Pattern
Bridging is resist connecting lines that should stand separate; missing pattern is the opposite, features absent or broken where the design puts them. Both are usually exposure and focus errors made visible at develop, and they transfer directly: a bridge etches as a short, a broken line as an open. Single-line and multi-line opens were the motivating defect class for early PDI work, including the pattern-defect study that remains the most cited paper on the gate.
Pattern Collapse
Photoresist pattern collapse is tall, narrow resist lines pulled over by capillary forces as the rinse liquid dries between them. The risk scales with aspect ratio, which makes collapse a signature problem of advanced nodes, where resist lines are far taller than they are wide. A collapsed line cannot be etched correctly anywhere along its length, and collapse often takes neighboring lines with it, so it reads as a regional defect rather than a point.
Developer Residue and Stains
Developer residue is byproduct from the develop and rinse chemistry left on the pattern: stains, satellite spots and drying marks. It is a develop-stage cousin of the coating defects caught one gate earlier, and the boundary is simple: anything present before exposure belongs to the coat check, anything deposited by develop and rinse belongs here.
Hotspots Revealed at Develop
Hotspots are marginal features at the edge of the exposure window that print thinned, necked or deformed, and first become visible as developed resist. They are the clearest case of a defect made at the scanner and caught at PDI, and the reason PDI results feed back to focus and dose settings as well as to the develop track.
Macro and Micro: How PDI Is Run
PDI runs in two layers: macro defect inspection scans the whole wafer for large-area signatures, and micro inspection resolves pattern-level defects die by die. The two layers answer different questions at different speeds, and a production develop gate uses both.
Macro Defect Inspection
Macro defect inspection images the entire developed wafer at once, looking for the signatures that cover regions rather than points: scumming zones, collapse fields, missing-pattern areas, comets and gross develop non-uniformity. It is fast enough to run at track throughput, which is why macro inspection is often integrated with the litho cell itself and run on every wafer rather than a sample. When a develop excursion hits, a developer batch fading or a rinse problem spreading, the macro layer is where it shows first.
Micro Patterned Inspection
Micro inspection compares die against die on the developed pattern to find the pattern-level defects macro imaging cannot resolve: individual bridges, line opens and local collapse. Brightfield optical inspection carries most of this load, and its limits define the layer’s economics: at fine pitch and low resist contrast, small opens fall below what optics resolves, and e-beam inspection picks them up at the cost of throughput and careful management of resist shrinkage under the beam. E-beam at PDI is therefore a sampling tool, pointed at known-risk patterns, not a full-wafer scan.
Review and the Go/No-Go Call
Flagged sites from both layers go to review imaging, where each detection is confirmed and the wafer’s disposition is decided: release to etch, rework, or hold for engineering. The gate’s output is that call, made per wafer on a track-speed clock, and everything about the gate’s value concentrates in how good the call is.
The split in one line: macro sees the wafer, micro sees the die, and review sees the defect.
The Last Free Rework Gate
PDI is the last point in the build cycle where a patterning defect costs only resist: strip the wafer, clean it, recoat and re-expose, and nothing is lost but a track pass. The pattern exists purely in a sacrificial layer, so the wafer underneath is untouched by the mistake.
That stops being true one step later. A defect that escapes PDI is etched into the layer, and the dies it crosses are gone; by final test, the same defect has consumed the full fabrication sequence, dicing and packaging before it is found. The cost of one escaped develop defect is not fixed, it compounds with every step it survives, and PDI is the gate standing where the price is still at its floor.
The economics cut in both directions, which is what makes the gate’s judgment the hard part. A false reject sends a good wafer through an unnecessary strip and recoat, burning track time and cycle time for nothing. A miss commits a defective pattern to etch. Every develop gate runs between those two costs, and where it lands depends on how consistently detections are judged, wafer after wafer, shift after shift.
The ladder is the gate’s argument in one frame: the defect does not change, only the price of finding it does.
Where AI Review Fits at the PDI Gate
AI defect review applies automated judgment to the images PDI tools already produce: classifying each detection and supporting the go/no-go call at track speed. The gate’s bottleneck is rarely detection, macro and micro layers flag plenty. It is the review queue, where flagged sites wait for a judgment, and where that judgment’s consistency decides both the false rework rate and the escapes.
Classification sorts upstream of the call: real scumming, bridges and collapse separated from nuisance detections before anyone dispositions a wafer. Review automation then applies the same judgment standard to every wafer, so the release decision does not drift with the shift, the operator or the backlog.
Averroes.ai runs as an overlay on the macro, micro and review tools already installed at the develop gate. AI defect review applies automated judgment on review images, with AI defect classification sorting detections ahead of it, trained from 20 to 40 labeled images per defect class, with no code, deployed on premise so wafer image data stays inside the fab. It augments the installed inspection tools; it does not replace them.
Rework or Release, Before Etch Decides for You?
See AI defect review on your own post-develop inspection images
Frequently Asked Questions
What is post-develop inspection in semiconductor manufacturing?
Post-develop inspection (PDI) is the semiconductor manufacturing gate that checks the developed photoresist pattern before etch. It catches scumming, bridging, pattern collapse, missing pattern and residue while the pattern exists only in resist, so a failing wafer can still be stripped, recoated and re-exposed instead of scrapped.
Is PDI the same as ADI?
Yes. Post-develop inspection and after develop inspection name the same gate: the defect check on developed resist before etch commit. PDI is the more common term in fab operations, while ADI appears in litho-cell and metrology contexts, especially in the phrase ADI CD for linewidth measured on developed resist.
What is the difference between PDI and AEI?
PDI inspects the pattern while it exists only in photoresist, before etch, so a failing wafer can be reworked. AEI, after-etch inspection, checks the pattern once it has been transferred into the layer below, where defects are permanent. PDI gates the decision to etch; AEI verifies what the etch actually did.
What is resist scumming?
Resist scumming is residual photoresist left in areas that should have developed completely clear. It comes from under-develop, weak or exhausted developer, or under-exposure, and it matters because a scummed space etches as a blocked or narrowed feature. Scumming across a region usually points at the developer or the develop recipe.
What causes photoresist pattern collapse?
Photoresist pattern collapse happens when capillary forces from the rinse liquid pull tall, narrow resist lines over as they dry. The risk rises with aspect ratio, so collapse is worst at advanced nodes where lines are much taller than they are wide. A collapsed line cannot transfer correctly at etch anywhere along its length.
Can a wafer that fails PDI be reworked?
Yes, and it is the only patterning gate where this is true. The defective pattern exists only in photoresist, so the wafer is stripped, cleaned, recoated and re-exposed, at the cost of one pass through the litho track. After etch the pattern is cut into the layer itself, and rework is no longer possible.
Post-develop inspection (PDI), also called after-develop inspection (ADI), is the inline check of the developed photoresist pattern before etch in semiconductor manufacturing. It catches the defects develop creates or reveals, scumming, bridging, pattern collapse, missing pattern and residue, while the pattern still exists only in resist. A wafer that fails PDI can be stripped, recoated and re-exposed; the same defect found after etch is permanent. That is what makes PDI the gate that decides etch commit.
PDI is the middle gate of the Stage 03 inspection chain in the semiconductor manufacturing process, between the resist coat check and post-etch inspection. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps the develop defects, the macro and micro methods that catch them, and the economics that make this gate’s judgment worth more than any other in the patterning loop.
Key Notes
PDI, ADI and the Three-Gate Chain
Post-develop inspection and after-develop inspection name the same gate: PDI is the common term in fab operations, ADI in litho-cell and metrology contexts. Both mean the defect check that runs once the exposed resist image has been developed into a physical pattern, and both end in the same decision: release the wafer to etch, rework it, or hold it.
The gate sits in the middle of a chain of three. Photoresist inspection checks the coated film before exposure, so coating defects never reach the scanner. PDI checks the developed pattern before etch, which this page covers. Post-etch inspection verifies the transferred pattern after it, when rework is no longer possible. Each gate exists because the step before it can fail in ways the step after it makes permanent.
Two measurements run on the same developed wafer and get blended into PDI, and neither belongs to it. Overlay, the alignment of this layer’s pattern to the one below, is measured by overlay metrology on dedicated targets; a misaligned wafer is a metrology finding, not an inspection detection, even though it triggers the same rework. And ADI CD, the linewidth measurement on developed resist, belongs to critical dimension metrology. PDI is the defect side of the develop check: it answers whether the pattern is intact, not how wide or how aligned it is.
Develop itself is the final step of the photolithography process, and PDI inspects its output. Everything the exposure and develop sequence can get wrong converges on this one surface.
Develop defects at a glance
The chain makes the gate’s position visible: PDI is the last point where the loop still runs backward. Past etch, the arrow only points forward.
What Defects Does Develop Create or Reveal?
Develop defects are flaws in the resist pattern that appear when the exposed image is developed: some created by the develop step itself, some printed earlier at the scanner and first visible now. Both kinds surface on the same wafer at the same gate, which is why PDI data feeds back in two directions.
The gallery carries the section’s split: some of these defects were made at develop, and some were made at exposure and only became visible here.
Resist Scumming and Incomplete Develop
Resist scumming is residual resist left in spaces that should have developed clear. It comes from under-develop, exhausted or weak developer, insufficient develop time, or under-exposure that left the resist less soluble than intended. A scummed space etches as a blocked or narrowed feature, so a contact hole with scum at its base becomes a failed connection one step later.
Bridging and Missing Pattern
Bridging is resist connecting lines that should stand separate; missing pattern is the opposite, features absent or broken where the design puts them. Both are usually exposure and focus errors made visible at develop, and they transfer directly: a bridge etches as a short, a broken line as an open. Single-line and multi-line opens were the motivating defect class for early PDI work, including the pattern-defect study that remains the most cited paper on the gate.
Pattern Collapse
Photoresist pattern collapse is tall, narrow resist lines pulled over by capillary forces as the rinse liquid dries between them. The risk scales with aspect ratio, which makes collapse a signature problem of advanced nodes, where resist lines are far taller than they are wide. A collapsed line cannot be etched correctly anywhere along its length, and collapse often takes neighboring lines with it, so it reads as a regional defect rather than a point.
Developer Residue and Stains
Developer residue is byproduct from the develop and rinse chemistry left on the pattern: stains, satellite spots and drying marks. It is a develop-stage cousin of the coating defects caught one gate earlier, and the boundary is simple: anything present before exposure belongs to the coat check, anything deposited by develop and rinse belongs here.
Hotspots Revealed at Develop
Hotspots are marginal features at the edge of the exposure window that print thinned, necked or deformed, and first become visible as developed resist. They are the clearest case of a defect made at the scanner and caught at PDI, and the reason PDI results feed back to focus and dose settings as well as to the develop track.
Macro and Micro: How PDI Is Run
PDI runs in two layers: macro defect inspection scans the whole wafer for large-area signatures, and micro inspection resolves pattern-level defects die by die. The two layers answer different questions at different speeds, and a production develop gate uses both.
Macro Defect Inspection
Macro defect inspection images the entire developed wafer at once, looking for the signatures that cover regions rather than points: scumming zones, collapse fields, missing-pattern areas, comets and gross develop non-uniformity. It is fast enough to run at track throughput, which is why macro inspection is often integrated with the litho cell itself and run on every wafer rather than a sample. When a develop excursion hits, a developer batch fading or a rinse problem spreading, the macro layer is where it shows first.
Micro Patterned Inspection
Micro inspection compares die against die on the developed pattern to find the pattern-level defects macro imaging cannot resolve: individual bridges, line opens and local collapse. Brightfield optical inspection carries most of this load, and its limits define the layer’s economics: at fine pitch and low resist contrast, small opens fall below what optics resolves, and e-beam inspection picks them up at the cost of throughput and careful management of resist shrinkage under the beam. E-beam at PDI is therefore a sampling tool, pointed at known-risk patterns, not a full-wafer scan.
Review and the Go/No-Go Call
Flagged sites from both layers go to review imaging, where each detection is confirmed and the wafer’s disposition is decided: release to etch, rework, or hold for engineering. The gate’s output is that call, made per wafer on a track-speed clock, and everything about the gate’s value concentrates in how good the call is.
The split in one line: macro sees the wafer, micro sees the die, and review sees the defect.
The Last Free Rework Gate
PDI is the last point in the build cycle where a patterning defect costs only resist: strip the wafer, clean it, recoat and re-expose, and nothing is lost but a track pass. The pattern exists purely in a sacrificial layer, so the wafer underneath is untouched by the mistake.
That stops being true one step later. A defect that escapes PDI is etched into the layer, and the dies it crosses are gone; by final test, the same defect has consumed the full fabrication sequence, dicing and packaging before it is found. The cost of one escaped develop defect is not fixed, it compounds with every step it survives, and PDI is the gate standing where the price is still at its floor.
The economics cut in both directions, which is what makes the gate’s judgment the hard part. A false reject sends a good wafer through an unnecessary strip and recoat, burning track time and cycle time for nothing. A miss commits a defective pattern to etch. Every develop gate runs between those two costs, and where it lands depends on how consistently detections are judged, wafer after wafer, shift after shift.
The ladder is the gate’s argument in one frame: the defect does not change, only the price of finding it does.
Where AI Review Fits at the PDI Gate
AI defect review applies automated judgment to the images PDI tools already produce: classifying each detection and supporting the go/no-go call at track speed. The gate’s bottleneck is rarely detection, macro and micro layers flag plenty. It is the review queue, where flagged sites wait for a judgment, and where that judgment’s consistency decides both the false rework rate and the escapes.
Classification sorts upstream of the call: real scumming, bridges and collapse separated from nuisance detections before anyone dispositions a wafer. Review automation then applies the same judgment standard to every wafer, so the release decision does not drift with the shift, the operator or the backlog.
Averroes.ai runs as an overlay on the macro, micro and review tools already installed at the develop gate. AI defect review applies automated judgment on review images, with AI defect classification sorting detections ahead of it, trained from 20 to 40 labeled images per defect class, with no code, deployed on premise so wafer image data stays inside the fab. It augments the installed inspection tools; it does not replace them.
Rework or Release, Before Etch Decides for You?
See AI defect review on your own post-develop inspection images
Frequently Asked Questions
What is post-develop inspection in semiconductor manufacturing?
Post-develop inspection (PDI) is the semiconductor manufacturing gate that checks the developed photoresist pattern before etch. It catches scumming, bridging, pattern collapse, missing pattern and residue while the pattern exists only in resist, so a failing wafer can still be stripped, recoated and re-exposed instead of scrapped.
Is PDI the same as ADI?
Yes. Post-develop inspection and after develop inspection name the same gate: the defect check on developed resist before etch commit. PDI is the more common term in fab operations, while ADI appears in litho-cell and metrology contexts, especially in the phrase ADI CD for linewidth measured on developed resist.
What is the difference between PDI and AEI?
PDI inspects the pattern while it exists only in photoresist, before etch, so a failing wafer can be reworked. AEI, after-etch inspection, checks the pattern once it has been transferred into the layer below, where defects are permanent. PDI gates the decision to etch; AEI verifies what the etch actually did.
What is resist scumming?
Resist scumming is residual photoresist left in areas that should have developed completely clear. It comes from under-develop, weak or exhausted developer, or under-exposure, and it matters because a scummed space etches as a blocked or narrowed feature. Scumming across a region usually points at the developer or the develop recipe.
What causes photoresist pattern collapse?
Photoresist pattern collapse happens when capillary forces from the rinse liquid pull tall, narrow resist lines over as they dry. The risk rises with aspect ratio, so collapse is worst at advanced nodes where lines are much taller than they are wide. A collapsed line cannot transfer correctly at etch anywhere along its length.
Can a wafer that fails PDI be reworked?
Yes, and it is the only patterning gate where this is true. The defective pattern exists only in photoresist, so the wafer is stripped, cleaned, recoated and re-exposed, at the cost of one pass through the litho track. After etch the pattern is cut into the layer itself, and rework is no longer possible.