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Semiconductor Inspection & Metrology Explained

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Averroes
Apr 10, 2026
Semiconductor Inspection & Metrology Explained

Semiconductor inspection finds and locates defects on wafers, masks, and packages. Semiconductor metrology measures process parameters like CD, overlay, and film thickness against target. Fabs need both, because each catches failures the other cannot see.

At advanced nodes, the margin for error is essentially gone.

A defect missed, a parameter drifted, a tool slowly out of calibration: any of these compounds across hundreds of subsequent steps.

Semiconductor inspection and metrology are how fabs stay in control of a process that’s trying to escape it. Here’s a complete breakdown of both – tools, methods, process control, and the role of AI.

This guide is part of our semiconductor manufacturing hub.

Key Notes

  • Inspection and metrology solve different problems – neither can substitute for the other.
  • Semiconductor defect inspection spans four distinct targets: bare wafer, patterned wafer, mask, and packaging.
  • At advanced nodes, rule-based inspection tools are hitting a ceiling – AI closes the gap.

What Is Semiconductor Inspection?

A semiconductor inspection system scans wafers, masks, and packaged devices to find, locate, and classify physical defects before they reach yield or reliability; wafer inspection is the largest category.

Semiconductor inspection answers one question: where are the defects, and what are they?

It’s an active scan of wafers, reticles, or packaged devices to find physical anomalies that threaten yield or reliability. The output is categorical – defect maps, defect density counts, defect type classifications, and pareto breakdowns by mechanism. 

It tells you something went wrong and where.

Semiconductor inspection stages: incoming wafer, critical FEOL/BEOL layers, mask and reticle, and packaging

Inspection Is Deployed At Multiple Stages

  • Incoming wafer – catching surface defects and particles before patterning begins
  • Critical FEOL/BEOL layers – after etch, deposition, CMP, and cleans where defect risk is highest
  • Post-mask/reticle steps – before errors on the mask replicate across every die
  • Post-assembly and packaging – catching cracks, voids, mis-bonds, and TSV defects before a bad package ships

The defining characteristic of inspection is that it catches things you didn’t predict. Rule violations, tool excursions, contamination events – these don’t announce themselves. Inspection is how you find them.

What Is Semiconductor Metrology?

Semiconductor metrology is the measurement of wafer parameters, such as critical dimension, overlay, and film thickness, against their targets, with known measurement uncertainty. The results feed SPC charts and process controllers that keep each step centered within spec. Most of it is wafer metrology: measurements taken on product or monitor wafers between process steps.

Semiconductor metrology answers a different question: what exactly are the dimensions and properties, and how far are they from target?

Where inspection finds defects, semiconductor metrology measures parameters. The output is continuous and quantitative – values with known uncertainty that feed SPC charts, APC loops, and run-to-run controllers. 

It tells you not just that something changed, but how much and in which direction.

Semiconductor metrology measurement categories: CD, overlay, film thickness, topography, electrical, and stress

Key Measurement Categories Include:

Metrology Type What It Measures Common Techniques
CD metrology Line widths, gate length, contact size CD-SEM, scatterometry, optical CD
Overlay Layer-to-layer misregistration (nm) Optical, e-beam overlay tools
Film thickness and composition Oxide, nitride, metal, resist thickness Ellipsometry, reflectometry, XRF
Surface topography Roughness, height maps AFM, optical profilometry
Electrical and materials Sheet resistance, dopant profiles Four-point probe, SIMS, XPS
Stress Wafer bow, warp, film stress Laser scanning, curvature tools

One Important Practical Note 

Metrology is sampled, not 100% coverage. 

Measuring every site on every wafer at every step is economically impossible. The discipline of metrology includes deciding where to measure and how often – a sampling strategy that balances process control confidence against throughput cost.

Semiconductor Inspection vs Metrology: Why You Need Both

The clearest way to distinguish them: inspection is defect-centric, metrology is parameter-centric. 

They’re solving different problems, and neither can substitute for the other.

What Each One Catches That The Other Misses

Inspection Metrology
Question answered Where are the defects, and what are they? How far is each parameter from target?
Output Categorical: defect maps, counts, classifications Continuous: values with known uncertainty
Coverage Broad scans at high throughput Sampled sites, set by a sampling strategy
Typical tools Brightfield, darkfield, e-beam, X-ray CD-SEM, scatterometry, ellipsometry, overlay tools
Catches what the other misses Random excursions, particles, pattern breaks, contamination events Slow drift in CD, overlay, and film thickness
Feeds Excursion control, lot holds, root cause SPC charts, APC and run-to-run controllers
What inspection catches that metrology misses, and what metrology catches that inspection misses

Why Neither Can Replace The Other Practically

Metrology can’t scale to replace inspection

  • Slower per measurement site and more expensive to run at high coverage
  • Sometimes destructive or semi-destructive – unsuitable for production wafers at volume
  • Miscalibrated as a defect-detection tool: it isn’t built to catch random, sudden excursions

Inspection can’t scale to replace metrology

  • No calibrated, quantitative output – it tells you that something is wrong, not how far from spec
  • Struggles with the subtle, nanometer-level parametric shifts that matter most at advanced nodes
  • Can’t drive APC or R2R controllers without continuous numeric feedback

The consequence of dropping either one is concrete

  • Without inspection, a catastrophic excursion (a mis-recipe, a contaminated tool, a damaged mask) moves through 1,000+ process steps undetected at advanced nodes. 
  • Without metrology, you have no quantitative feedback to correct what inspection flags. You’re screening bad wafers out rather than fixing the process that made them bad.

Modern fabs co-optimize both, placing inspection and metrology at critical locations across the process stack to minimize scrap, enable fast root cause, and hold tight design margins.

Types of Semiconductor Inspection

Semiconductor inspection methods vary by what’s being inspected and what imaging physics is doing the detection.

Semiconductor inspection types by target and by imaging technology

By Target/Substrate:

  • Bare wafer inspection – laser-scatter systems map particles and surface defects on incoming wafers before patterning, and monitor tool-induced contamination
  • Patterned wafer defect inspection – the most intensive category; brightfield, darkfield, and e-beam tools compare dies or use modeling to find pattern defects in-process
  • Mask/reticle inspection – optical and e-beam systems check EUV/DUV masks, because any defect on the mask prints on every die it exposes
  • Post-assembly/packaging inspection – optical and X-ray catch cracks, voids, wire bond failures, and TSV defects at the package level

By Imaging Technology

  • Optical brightfield – high throughput, good for large defects, sensitive to pattern variations; workhorse for patterned wafer inspection
  • Optical darkfield – better sensitivity for particles and surface defects on unpatterned or lightly patterned wafers
  • Electron beam (e-beam) – highest sensitivity for sub-10nm defects and electrical defects; slow throughput, typically used on critical layers or as a review tool
  • X-ray / CT – non-destructive imaging through package materials; essential for advanced packaging
  • Acoustic/ultrasonic – detects delamination and voids in bonded stacks and package substrates

Inline vs Offline Is The Other Key Dimension

Inline inspection happens on the production line and provides real-time feedback, but must balance sensitivity against throughput. Offline or review tools trade speed for resolution – used to confirm and characterize what inline tools flag.

Types of Semiconductor Metrology

Semiconductor metrology falls into four families: CD and dimensional metrology, overlay metrology, film thickness and composition metrology, and electrical and materials metrology.

Wafer metrology spans several distinct measurement disciplines, each targeting different process parameters with different physics.

Types of semiconductor metrology: CD and dimensional, overlay, film thickness and composition, electrical and materials

CD & Dimensional Metrology 

The backbone of lithography and etch control.

  • CD-SEM – measures line and space widths directly from SEM images
  • Scatterometry (optical CD) – reconstructs CD, profile, and sidewall angle from diffraction signals; faster than SEM and suitable for inline monitoring at scale

Overlay Metrology 

Overlay metrology measures layer-to-layer alignment in nanometers. 

At advanced nodes, overlay budgets are in single digits. Even small misregistration causes via misses, shorts, or opens – yield-killing failures that don’t always surface immediately.

Film Thickness & Composition 

Covers the full range of deposited and grown layers: gate oxides, barrier metals, low-k dielectrics, photoresist.

  • Ellipsometry & reflectometry – standard for dielectric and resist films
  • XRF & XRR (X-ray techniques) – handle metals and ultra-thin layers

Electrical & Materials Metrology 

Connects physical measurements to electrical device performance.

  • 4-point probe – sheet resistance
  • SIMS – dopant depth profiles
  • XPS – surface chemistry

Inline vs Offline Metrology: Definitions

Inline metrology measures wafers on the production line between process steps, fast enough to feed run-to-run control without holding the lot. Offline metrology and analysis happen in a lab or review area, where slower, higher-resolution, and sometimes destructive techniques confirm and characterize what inline tools flag. Most fabs run both.

Inline Metrology Offline Analysis In-Situ and Virtual Metrology
Where On the production line Lab or review area Inside the process tool, or predicted from its sensors
Speed Fast, sampled Slow, detailed Real-time
Role Process control feedback Root cause and characterization Continuous coverage between physical samples
Examples Scatterometry, ellipsometry, overlay tools Cross-section SEM, TEM, SIMS Optical emission sensing, virtual metrology

The Unifying Principle Across All Wafer Metrology 

Every measurement carries uncertainty, and that uncertainty must be small relative to the process window. As nodes shrink, so does the window – and so must the measurement uncertainty.

Semiconductor Inspection Equipment: What to Know

The major players in semiconductor inspection and metrology equipment – KLA, Applied Materials, Onto Innovation, ASML, Hitachi, Zeiss, Lasertec – build tools that can cost millions of dollars per unit. 

Selecting the right equipment involves more than sensitivity specs.

Semiconductor inspection and metrology equipment categories and leading vendors

Who Makes The Tools

Category Example Vendors
Optical wafer inspection (patterned and bare) KLA, Applied Materials, Hitachi High-Tech
E-beam inspection and review Applied Materials, KLA, ASML, Hitachi High-Tech
Mask and reticle inspection KLA, Lasertec, Zeiss
CD and overlay metrology KLA, Hitachi High-Tech, ASML, Onto Innovation
Film and composition metrology KLA, Onto Innovation

For tool-by-tool comparisons, see our guides to wafer inspection tools and semiconductor metrology tools.

The Hidden Cost Of False Positives Deserves Emphasis

Every false positive triggers reinspection, engineer review, and potential hold decisions on good wafers. 

At scale, this translates to hundreds of hours of wasted labor per month per application – a measurable throughput and cost hit that often goes unexamined in equipment evaluations.

How Semiconductor Inspection and Metrology Data Feed Process Control

Data from semiconductor inspection and metrology doesn’t just sit in reports. It drives active process control across the fab.

Here’s a look at the control stack:

SPC (Statistical Process Control)

The first filter. Metrology and inspection outputs are charted against control limits.

  • In-control measurements pass forward as valid feedback to APC
  • Out-of-control signals trigger engineering escalation
  • Critically: blocks APC controllers from making corrections on bad data

APC & Run-to-Run (R2R) Control 

Uses valid metrology measurements to update process recipes for the next wafer or lot.

  • Lithography – R2R adjusts focus and dose based on overlay and CD feedback
  • CMP – adjusts polish time based on film thickness measurements
  • Accounts for tool-specific biases and disturbances to keep every tool centered within spec

FDC (Fault Detection and Classification)

Works from tool sensor traces rather than wafer measurements – detecting abnormal tool states in real time.

  • Flags faults before more wafers are exposed to the problem
  • Lots can be held and recipes frozen immediately on detection

Virtual Metrology 

Predicts metrology outcomes from process tool sensor data, extending coverage between physical sampling points. Averroes delivers this as a virtual metrology layer on existing tools; our virtual metrology guide covers methods and ROI.

  • Estimates what CD or film thickness would be – without a physical measurement
  • Tighter process control without increasing measurement cost or sampling frequency

When Inspection Triggers APC Action

  • A defect excursion → automatic tool containment or recipe hold
  • Increased metrology sampling on affected layers and tools
  • Controller limit adjustments if a defect mechanism links to an over-aggressive recipe (e.g., pattern collapse from CD pushed too tight)
How inspection and metrology data feed SPC, APC and run-to-run control, FDC, and virtual metrology

Challenges At Advanced Nodes

Semiconductor defect inspection and metrology are getting harder in direct proportion to how ambitious the chips are getting.

Shrinking Process Windows 

At 2nm and below, the gap between allowable parameter variation and tool measurement uncertainty is closing fast.

  • Metrology tool uncertainty must itself be in fractions of a nanometer
  • If it isn’t, the measurement system is consuming most of your process budget

High-NA EUV 

New mask complexity, new defect types, new sensitivity requirements – all at once.

  • Defect types that were irrelevant at previous nodes become yield-critical
  • Current optical and e-beam inspection is being pushed to its limits

Signal-to-Noise at Scale 

Detecting sub-10nm defects without generating a flood of false positives requires discrimination that rule-based tools increasingly cannot provide.

Tool Matching Across a Fleet 

If two CD or overlay tools read different values on the same wafer, SPC limits, APC controllers, and yield correlations all break.

  • Requires rigorous gauge R&R analysis and certified reference standards
  • Often demands continuous automated fleet-offset calibration on real production wafers
  • Must hold consistent baselines across tool generations, vendors, and years

The Role of AI in Semiconductor Inspection

Rule-based inspection tools work by comparing against known signatures or thresholds. 

At advanced nodes, that approach hits a ceiling: defect signatures are too varied, too subtle, and too numerous for static rules to handle at scale without either missing real defects or drowning the process in false positives.

AI Changes The Equation In A Few Specific Ways

  • Fewer false positives: models learn the difference between real defects and nuisance variation, cutting reinspection and engineer review.
  • Novel defects caught: unsupervised anomaly detection flags signatures no rule was written for.
  • Little training data needed: 20–40 images per defect class instead of thousands.
  • Consistent classification: the same criteria on every wafer, every shift, every tool.
  • No new hardware: AI runs as a software layer on the inspection tools a fab already owns.
How AI improves semiconductor inspection: fewer false positives, novel-defect detection, few-shot training

What Averroes Delivers By The Numbers

  • Classification accuracy: 99%+
  • Object detection accuracy: 98.5%+
  • Segmentation accuracy: 97%+
  • False positive rate: near-zero
  • Training data required: ~20–40 images per defect class

These aren’t targets – they’re what we ship at.

And none of it requires replacing your existing capital equipment. Averroes runs on existing KLA, AOI, Onto, and other proprietary tools as a software layer – no new hardware, no process disruption, no additional capex. 

You get AI-grade inspection performance on the line you already have, from day one.

Could Your Current Line Catch More?

See AI inspection running on your existing equipment – no hardware changes.

 

Frequently Asked Questions

What is the difference between wafer inspection and wafer metrology? 

Wafer inspection detects the presence and location of defects – particles, pattern breaks, voids – and returns categorical outputs like defect maps and counts. Wafer metrology measures specific process parameters – CD, overlay, film thickness – and returns continuous, quantitative values with known uncertainty. Both are required; neither substitutes for the other.

What equipment is used for semiconductor inspection? 

Semiconductor inspection equipment includes optical brightfield and darkfield systems, electron beam tools, X-ray and CT scanners, and acoustic/ultrasonic systems for packaging. Leading vendors include KLA, Applied Materials, Onto Innovation, Hitachi, and Zeiss. The right tool depends on the inspection target, required sensitivity, and throughput constraints.

How does metrology support yield improvement in semiconductor manufacturing? 

Metrology supports yield improvement by providing the quantitative feedback that keeps process parameters centered within spec across hundreds of manufacturing steps. Without it, systematic drift (in CD, overlay, or film thickness) accumulates undetected until parametric yield loss appears, often late and expensive to diagnose.

What is virtual metrology in semiconductor manufacturing? 

Virtual metrology predicts physical measurement outcomes – CD, film thickness, overlay – from process tool sensor data, extending process control coverage between physical sampling points. For methods, accuracy, and deployment, see our full guide to virtual metrology in semiconductor manufacturing.

Conclusion

Semiconductor inspection and metrology aren’t interchangeable disciplines. They’re complementary control systems solving fundamentally different problems. 

Inspection catches what you didn’t predict: the excursion, the contamination event, the mask defect replicating across every die. Metrology catches what you didn’t notice: the slow CD drift, the overlay creeping out of spec, the film thickness that looks fine until it isn’t. 

Drop either one, and you’re not just flying blind on defects or parameters – you’re losing the feedback loop that makes high-volume manufacturing at advanced nodes economically viable.

AI is where both disciplines are heading, not as a replacement for capital equipment but as the intelligence layer that makes existing tools perform at a level that rule-based approaches can no longer sustain. 

If you want to see what that looks like on your line – with your defect types, your equipment, your process – book a free demo with Averroes.

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